IBM Takes Server Memory to Another Level
IBM has come out with its plan to create a new open standard memory interface at the Hot Chips conference held in August. The new standard of memory will be able to interact with a wide range of memory devices instead of relying only on DDR.
The developments were announced as IBM held the presentation on their new Power9 scale up processer at the Hot Chips event. IBM has used the same chip in their E980 Enterprise server which was announced recently. The chip enables up to 16 sockets which translates to 192 cores with 32 PCIe Gen4 x16 slots and 64 TB memory. The products is aimed at industrial level database processing and similar workflows which require a lot of memory, compute threads, and I/O.
The servers can be very expensive for the form of scale-out cluster that are used in HPC shops. But they can be employed as fat memory nodes in the scale-out clusters. IBM has to offer the scale out Power9 which is meant for the IBM AC922 and two other socket servers. The same type of setup has been provided in the Summit supercomputer.
How Memory Helps Separate How The Power9 Chips Work?
The memory interface makes the biggest difference between the two Power9 chips. The scaled up version comes with higher memory capacity per socket- 8 TB compared to 2 TB. It also has improved memory bandwidth at 230 GB/sec compared to 150 GB/sec. The scale up chip achieves this feat by using SerDes links instead of connecting directly to DDR memory. The Differential Memory Interface (DMI) on IBM’s on-chip manages the SerDes links which then interacts with IBM’s Centaur memory buffer chips. The buffer chips are the ones to be linked with DDR DIMMs.
How Can the New Improvements Help?
The new improvement brings around 10ns more of latency for memory access than a DDR connection but also adds up to the size of the servers which is worth the trade off. The Centaur buffered memory takes help of the DDR memory chips for its storage media but soon the case may change as IBM has removed the DDR smarts from the chip.
IBM is going forward to generalize their memory interface which they would call as OpenCAPI memory. The new technology is going to be featured in the coming Power9 processor which hits the market in 2019. The new Power9 chips will be able to support mainstream systems and other two socket HPC servers. According to IBM, the new Power9 chips will be able to run over 350 GB/sec of memory bandwidth per each socket, which is going to be more than double the speed achieved by modern high-standard chips for two socket servers. IBM has also taken the steps to cut the latency penalty down to 5ns in its preliminary rounds.
IBM’s Big Bet on the OpenCAPI Memory
IBM has made big plans to establish OpenCAPI memory as the new open industry standard. They are looking to level the playing field with more innovation for memory devices with the brand of OpenCAPI. It follows the line of original OpenCAPI design which promised to do more for I/O devices. The simple concept is to enable processors to interact with any type of memory using the SerDes links. This way GPUs, CPUs and FPGAs will not have to connect to GDDR, DDR or other forms of memory technology.
It is not going to be easy for IBM to implement a new standard and we have to wait until the products roll out commercially to see if they live up to the hype.
